1. Field of the Invention
The present invention generally relates to a differential signaling transmitter, and more particularly, to a low power differential signaling transmitter.
2. Description of Related Art
For the purpose of improving a sensitivity and saving power consumption of electronic components, a differential input is often employed for amplifying a small amplitude so as to convey information therein in accordance with the value of the amplified amplitude, and transmitting as an information signal. Typically, a conventional differential signaling transmitter works when a power source voltage VDD is greater than 2.5V. However, when the power source voltage VDD is smaller than 2.0V (e.g., a 0.18 μm semiconductor processing requires a power source voltage of 1.8V), failures of the conventional differential signaling transmitter may be caused by a lack of headroom in the VDD direction. It is caused by a finite on-resistance of a PMOS transistor switch, and the finite on-resistance may generate a span voltage over the transistor and thus consumes the headroom. As such, a greater power source voltage is required for allowing the differential signaling transmitter to work normally.
FIG. 1 is a circuit diagram of a conventional differential signaling transmitter. Referring to FIG. 1, a conventional differential signaling transmitter 10 includes current sources 11, 13, an inverter switching circuit 12 and an impedance 14. The inverter switching circuit 12 includes two output terminals, OUTP and OUTN. The current source 11 is coupled to the inverter switching circuit 12, and the inverter switching circuit 12 is coupled to the current source 13. The impedance 14 has two terminals respectively coupled to the output terminals OUTP and OUTN of the inverter switching circuit 12.
The inverter switching circuit 12 includes transistors 120, 121, 123 and 124. The transistors 120 and 123 are PMOS transistors. The transistors 121 and 124 are NMOS transistors. The transistors 120 and 121 are coupled together and form a first inverter. The transistors 123 and 124 are coupled together and form a second inverter. The first inverter receives a first input voltage VINP, and the second inverter receives a second input voltage VINN. The current sources 11 and 13 are controlled by the bias signals BP and BN respectively, and provide currents to the inverter switching circuit 12, respectively.
When the first input voltage VINP is at a high voltage level, and the second input voltage VINN is relatively at a low voltage level, the transistors 123 and 121 are turned on, and the transistors 120 and 124 are cut off, and in this case the current flows from the transistor 123 to the impedance 14 and then flows to the transistor 121. Therefore, a differential voltage signal conformed at the output terminals OUTP and OUTN is equal to a product of the current value flowing through the impendence 14 and the resistance of the impendence 14. The difference between the output terminals OUTP and OUTN is positive in this case.
Otherwise, when the first input voltage VINP is at a low voltage level, and the second input voltage VINN is at a high voltage level relatively, the transistors 120 and 124 are turned on, and the transistors 121 and 123 are cut off, and in this case the current flows from the transistor 120 to the impedance 14 and then flows to the transistor 124. Therefore, a differential voltage signal conformed at the output terminals OUTP and OUTN is equal to a product of the current value flowing through the impendence 14 and the resistance of the impendence 14. The difference between the output terminals OUTP and OUTN is negative in this case.
As discussed above, the conventional differential signaling transmitter works when a power source voltage VDD is greater than 2.5V, but may fail to work when the power source voltage VDD is smaller than 2V due to a lack of headroom in the direction of VDD. For resolving this problem, U.S. Patent Application No. 2004/0150434 provides a low voltage differential signaling (LVDS) driving apparatus. Comparing to the differential signaling transmitter 10 of FIG. 1, the LVDS driving apparatus does not include a current source, and therefore, the headroom can be reduced. The LVDS driving apparatus employs a reference current control circuit to provide a plurality of reference voltages for a plurality of gates of transistor switches. Each of the transistor switches includes a PMOS transistor and a NMOS transistor. Each of the transistor switches can be turned on by coupling their gates to the reference voltages, and can be cut off by switching the gate of the PMOS transistor to be coupled to the voltage VDD or switch the gate of the NMOS transistor to be coupled to a ground terminal GND.
FIG. 2 is a circuit diagram of the LVDS driving apparatus 20 of U.S. Patent Application No. 2004/0150434. Referring to FIG. 2, the apparatus 20 includes a switch control circuit 21, a reference current control circuit 30, a switch circuit 22, a differential signal output circuit 23, a resistor 25, and a differential amplifier 24. The switch circuit 22 is coupled to the reference current control circuit 30 and the switch control circuit 21. The differential signal output circuit 23 is coupled to the switch circuit 22. The resistor 25 has two terminals respectively coupled to two output terminals of the differential signal output circuit 23. The differential amplifier 24 has two input terminals respectively coupled to the two terminals of the resistor 25.
The switch control circuit 21 is adapted for providing switch control signals S1 and S2. The reference current control circuit 30 is adapted for generating a first reference voltage V1 and a second reference voltage V2. The switch circuit 22 generates a span voltage over the two terminals of the resistor 25 coupled thereto, according to the switch control signals S1 and S2. The differential amplifier 24 amplifies the span voltage over the two terminals of the resistor 25.
As shown in FIG. 2, the switch circuit 22 includes switches 220, 221, 222, 223, 224, 225, 226, and 227. The switches 220, 223, 225, and 226 are controlled by the control signal S2, and the switches 221, 222, 224, and 227 are controlled by the control signal S1. One terminal of the switch 220 is used for receiving a first reference voltage V1, and another terminal of the switch 220 is coupled to the switch 221. One terminal of the switch 222 is used for receiving a second reference voltage V2, and another terminal of the switch 222 is coupled to the switch 223. One terminal of the switch 224 is used for receiving the first reference voltage V1, and another terminal of the switch 224 is coupled to the switch 225. One terminal of the switch 226 is used for receiving the second reference voltage V2, and another terminal of the switch 226 is coupled to the switch 227.
The differential signal output circuit 23 includes transistors 230, 231, 232, and 233. The transistors 230 and 232 are PMOS transistors, while the transistors 231 and 233 are NMOS transistors. A gate of the transistor 230 is coupled to the switches 221 and 220. A gate of the transistor 231 is coupled to the switches 222 and 223. A gate of the transistor 232 is coupled to the switches 224 and 225. A gate of the transistor 233 is coupled to the switches 227 and 226.
When the control signal S2 is at a high level, and the control signal S1 is at a low level, the switches 220, 223, 225 and 226 are turned on, and the switches 221, 222, 224, and 227 are cut off. In this case, the gate voltage of the transistor 230 is the first reference voltage V1, and the gate voltage of the transistor 232 is the voltage VDD. The gate voltage of the transistor 231 is the ground GND, and the gate voltage of the transistor 233 is the second reference voltage V2. By designing the reference current control circuit 30 to generate the first reference voltage V1, the second reference voltage V2, the transistors 230 and 233 are turned on and the transistors 231 and 232 are cut off. As such, the current passing by the transistor 25 is flowing upwardly, and the value of the differential voltage amplified by the differential amplifier 24 is negative.
On the contrary, when the control signal S2 is at a low level, and the control signal S1 is at a high level, the switches 220, 223, 225 and 226 are cut off, and the switches 221, 222, 224, and 227 are turned on. In this case, the gate voltage of the transistor 230 is the voltage VDD, and the gate voltage of the transistor 232 is the first reference voltage V1. The gate voltage of the transistor 231 is the second reference voltage V2, and the gate voltage of the transistor 233 is the ground GND. By designing the reference current control circuit 30 to generate the first reference voltage V1, the second reference voltage V2, the transistors 231 and 232 are turned on and the transistors 230 and 233 are cut off. As such, the current passing by the transistor 25 flows downwards, and the value of the differential voltage amplified by the differential amplifier 24 is positive.
FIG. 3 is a circuit diagram illustrating the reference current control circuit 30. Referring to FIG. 3, the reference current control circuit 30 includes an operation amplifier 300, transistors 301, 304, 305, resistors 302, 303, and a current source 306. The transistors 304 and 305 are coupled together. The current source 306 is coupled to the transistor 305. The resistor 303 is coupled to the transistor 304. The resistor 302 is coupled to the transistor 301 and the resistor 303. A gate of the transistor 301 is coupled to an output terminal of the operation amplifier 300. The operation amplifier 300 includes a positive input terminal and a negative input terminal respectively coupled to the resistor 302 and a preset common mode voltage Vcm. The transistors 304 and 305 are PMOS transistors configuring a current mirror for generating the first reference voltage V1 which is sufficient for turning on the PMOS transistors 230 and 232. The current source 306 provides a current IREF to the current mirror, and the transistor 304 outputs a current IREF/n. The transistor 301 is an NMOS transistor. The transistor 301, the resistor 302, and the operation amplifier 300 form a negative feedback loop for generating the second reference voltage V2 which is sufficient for turning on the NMOS transistors 231 and 233. Generally, the reference current control circuit 30 generates the first reference voltage V1 and the second reference voltage V2, so as to control the differential signaling transmitter 20 to output a differential signal having a positive voltage value when the control signal S1 is at a high level, and the control signal S2 is at a low level; and output a differential signal having a negative voltage value when the control signal S1 is at a low level, and the control signal S2 is at a high level.
Further, U.S. Pat. No. 6,927,608 discloses another differential signaling transmitter which is named as a low power LVDS driver therein. The low power LVDS driver employs a switchable current source control circuit for generating a plurality of reference voltages to the gates of transistor switches. The gates of the transistor switches can be coupled to the reference voltages to turn on the transistor switches, or disconnected from the reference voltages to cut off the transistor switches. The gates of the transistor switches can be speeded up by introducing the active or passive pull up or down circuits, so as to allow the gates to achieve their ultimate voltages.
FIG. 4 is a circuit diagram of a differential signaling transmitter 40 provided by U.S. Pat. No. 6,927,608. Referring to FIG. 4, the transmitter 40 includes a current source 41, transistors 46, 47, impedance circuit 45, switchable current source control module 42, a first switchable current source 43, and a second switchable current source 44. The first switchable current source 43 is coupled to the switchable current source control module 42, the impedance circuit 45, and the transistor 46. The second switchable current source 44 is coupled to the switchable current source control module 42, the impedance circuit 45, and the transistor 47. The impedance circuit 45 has two terminals respectively coupled to the transistors 46 and 47. The current source 41 is coupled to the transistors 46 and 47.
The switchable current source control module 42 receives input voltages Vin_p and Vin_n, and generates control signals S1 and S2 according to the input voltages Vin_p and Vin_n. The first switchable current source 43 determines whether to generate a reference current ID according to the control signal S1, and the second switchable current source 44 determines whether to generate the reference current ID according to the control signal S2. The impedance circuit 45 is adapted for converting the reference current ID flowing therethrough into a differential voltage signal which is the difference of voltages at the two terminals Vout_p and Vout_n. The transistors 46 and 47 are respectively controlled by the input voltages Vin_p and Vin_n. The current source 41 provides the reference current ID.
When the input voltage Vin_p is at a high level, and the input voltage Vin_n is at a low level, the second switchable current source 44 generates the reference current ID, and the transistor 46 is turned on and the transistor 47 is cut off. Therefore, the reference current ID flows from the terminal Vout_p to the terminal Vout_n, and thus generating a differential voltage signal on the impedance circuit 45. When the input voltage Vin_p is at a low level, and the input voltage Vin_n is at a high level, the first switchable current source 43 generates the reference current ID, and the transistor 47 is turned on and the transistor 46 is cut off. Therefore, the reference current ID flows from the terminal Vout_n to the terminal Vout_p, and thus generating a differential voltage signal on the impedance circuit 45.
FIG. 5 is a circuit diagram of another differential signaling transmitter 50 provided by U.S. Pat. No. 6,927,608. Referring to FIG. 5, the transmitter 50 includes a current source 52, transistors 56 and 57, an impendence circuit 55, a switchable current source control module 51, a first switchable current source 53, a second switchable current source 54, a capacitor 58, and a common mode voltage regulation circuit 59. The first switchable current source 53 is coupled to the switchable current source control module 51, the impedance circuit 55, and the transistor 56. The second switchable current source 54 is coupled to the switchable current source control module 51, the impedance circuit 55, and the transistor 57. The impedance circuit 55 has two terminals Vout_p and Vout_n respectively coupled to the transistors 57 and 56. The current source 52 is coupled to the transistors 56 and 57. The capacitor 58 is coupled to the impedance circuit 55. The common mode voltage regulation circuit 59 is coupled to the impedance circuit 55.
The switchable current source control module 51 receives the input voltages Vin_p and Vin_n, and determines the reference current ID generated by the first switchable current source 53 or the second switchable current source 54 according to the input voltages Vin_p and Vin_n. The impedance circuit 55 is provided for converting the reference current ID flowing thereby into a differential voltage signal, which is the voltage difference between the two terminals Vout_p and Vout_n. The transistors 56 and 57 are respectively controlled by the input voltages Vin_p and Vin_n. The current source provides the reference current ID. The common mode voltage regulation circuit 59 is used for regulating the reference current ID provided by the current source 52, so as to allow a common mode voltage signal to achieve the desired voltage value.
The current source control module 51 includes an adjustable current mirror circuit 510, a buffer 511, and switches 512 and 513. The buffer 511 is coupled to the adjustable current mirror circuit 510, the switches 512 and 513. The adjustable current mirror circuit 510 receives an adjusting voltage Vadj, and generates a gate reference voltage Vgs_ref according to the adjusting voltage Vadj, and then provides the gate reference voltage Vgs_ref to the buffer 511. The buffer 511 outputs the gate reference voltage Vgs_ref to the switches 512 and 513. The switches 512 and 513 are respectively controlled by the input voltages Vin_p and Vin_n. When the input voltage Vin_p is at a high level, the gate reference voltage Vgs_ref will be outputted to the second switchable current source 54; and when the input voltage Vin_n is at a high level, the gate reference voltage Vgs_ref will be outputted to the first switchable current source 53.
The adjustable current mirror circuit 510 includes an amplifier 5101, a current source 5100, transistors 5102 and 5103. The current source 5100 is coupled to the transistors 5102 and 5103. The transistors 5102 and 5103 are coupled one to another. The amplifier 5101 is coupled to the transistors 5102 and 5103. The first switchable current source 53 includes a transistor 531 and an active pull up or down circuit 530. The transistor 531 is coupled to the active pull up or down circuit 530. The active pull up or down circuit 530 is provided for receiving the input voltage Vin_n. The second switchable current source 54 includes a transistor 541 and an active pull up or down circuit 540. The transistor 541 has a gate coupled to the active pull up or down circuit 540. The active pull up or down circuit 540 is provided for receiving the input voltage Vin_p. The active pull up or down circuits 530 and 540 are employed thereby mainly for the purpose of accelerating the switching speeds of the transistors 531 and 541, so as to compensate the delay caused by the buffer 511. The impedance circuit 55 includes two resistors 550 and 551. The resistor 550 is coupled to the resistor 551 and the capacitor 58. The common mode voltage regulation circuit 59 includes an amplifier 590 having two input terminals respectively coupled to the resistor 550 and a reference voltage signal VREF. The amplifier 590 further has an output terminal coupled to the current source 52.
When the input voltage Vin_p is at a high level, and the input voltage Vin_n is at a low level, the transistor 541 is turned on, and the second switchable current source 54 generates the reference current ID, the transistor 56 is turned on, and the transistor 57 is cut off. Meanwhile, the reference current ID flows from the terminal Vout_p to the terminal Vout_n, and generates a differential voltage signal at the impedance circuit 55. When the input voltage Vin_p is at a low level, and the input voltage Vin_n is at a high level, the transistor 531 is turned on, the first switchable current source 53 generates the reference current ID, the transistor 57 is turned on, and the transistor 56 is cut off. Meanwhile, the reference current ID flows from the terminal Vout_n to the terminal Vout_p, and generates a differential voltage signal at the impedance circuit 55.
FIG. 6 is a circuit diagram of still another differential signaling transmitter 60 provided by U.S. Pat. No. 6,927,608. Referring to FIG. 6, the transmitter 60 includes a current source 52, transistors 56 and 57, impedance circuit 55, a switchable current source control module 51, a first switchable current source 63, a second switchable current source 64, a capacitor 58, and a common mode voltage regulation circuit 59. FIG. 6 differs from FIG. 5 in that the first switchable current source 63 and the second switchable current source 64 of FIG. 6. The first and second switchable current sources operate with the passive pull up or down circuits, while those of FIG. 5 operate with the active pull up or down circuits. As to the principle of operation and the coupling layout of FIG. 6, they are similar as discussed above about FIG. 5, and are not to be described again hereby. As shown in FIG. 6, the first switchable current source 63 includes a capacitor 630, and a transistor 631. The transistor 631 has a gate coupled to the capacitor 630. The capacitor 630 is provided for receiving the input voltage Vin_p. The second switchable current source 64 includes a capacitor 640 and a transistor 641. The transistor 641 has a gate coupled to the capacitor 640. The capacitor 640 is provided for receiving the input voltage Vin_n. The capacitors 630 and 640 configure respectively the aforementioned pull up or down circuits.
In summary, U.S. Pat. No. 6,927,608, and U.S. Patent Application No. 2004/0150434 are all designed to use a control circuit for generating gate voltages for controlling the transistor switches. Therefore, in order to provide a better solution for the problems of the conventional differential signaling transmitters, a differential signaling transmitter is provided according to the present invention. The differential signaling transmitter is provided according to the present invention includes the switchable current sources, and the transistor switches are also served as the current sources.